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NXP Semiconductors /LPC11Exx /ADC /GDR

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Interpret as GDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0V_VREF0RESERVED0CHN0RESERVED 0 (OVERRUN)OVERRUN 0 (DONE)DONE

Description

A/D Global Data Register. Contains the result of the most recent A/D conversion.

Fields

RESERVED

Reserved. These bits always read as zeros.
V_VREF

When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.
RESERVED

Reserved. These bits always read as zeros.
CHN

These bits contain the channel from which the result bits V_VREF were converted.
RESERVED

Reserved. These bits always read as zeros.
OVERRUN

This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.
DONE

This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data